forked from cerc-io/plugeth
39 lines
1.7 KiB
Go
39 lines
1.7 KiB
Go
// Copyright 2018 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package cpu implements processor feature detection for
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// various CPU architectures.
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package cpu
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// CacheLinePad is used to pad structs to avoid false sharing.
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type CacheLinePad struct{ _ [cacheLineSize]byte }
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// X86 contains the supported CPU features of the
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// current X86/AMD64 platform. If the current platform
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// is not X86/AMD64 then all feature flags are false.
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//
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// X86 is padded to avoid false sharing. Further the HasAVX
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// and HasAVX2 are only set if the OS supports XMM and YMM
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// registers in addition to the CPUID feature bit being set.
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var X86 struct {
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_ CacheLinePad
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HasAES bool // AES hardware implementation (AES NI)
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HasADX bool // Multi-precision add-carry instruction extensions
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HasAVX bool // Advanced vector extension
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HasAVX2 bool // Advanced vector extension 2
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HasBMI1 bool // Bit manipulation instruction set 1
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HasBMI2 bool // Bit manipulation instruction set 2
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HasERMS bool // Enhanced REP for MOVSB and STOSB
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HasFMA bool // Fused-multiply-add instructions
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HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
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HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
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HasPOPCNT bool // Hamming weight instruction POPCNT.
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HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
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HasSSE3 bool // Streaming SIMD extension 3
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HasSSSE3 bool // Supplemental streaming SIMD extension 3
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HasSSE41 bool // Streaming SIMD extension 4 and 4.1
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HasSSE42 bool // Streaming SIMD extension 4 and 4.2
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_ CacheLinePad
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}
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