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Python Z3 proofs of the rules.
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31
test/formal/mod_add_to_addmod.py
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31
test/formal/mod_add_to_addmod.py
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@ -0,0 +1,31 @@
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from opcodes import MOD, ADD, ADDMOD
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from rule import Rule
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from z3 import BitVec
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"""
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Rule:
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MOD(ADD(X, Y), A) -> ADDMOD(X, Y, A)
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given
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A > 0
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A & (A - 1) == 0
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"""
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rule = Rule()
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n_bits = 32
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# Input vars
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X = BitVec('X', n_bits)
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Y = BitVec('Y', n_bits)
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A = BitVec('A', n_bits)
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# Non optimized result
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nonopt = MOD(ADD(X, Y), A)
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# Optimized result
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opt = ADDMOD(X, Y, A)
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rule.require(A > 0)
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rule.require(((A & (A - 1)) == 0))
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rule.check(nonopt, opt)
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31
test/formal/mod_mul_to_mulmod.py
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test/formal/mod_mul_to_mulmod.py
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@ -0,0 +1,31 @@
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from opcodes import MOD, MUL, MULMOD
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from rule import Rule
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from z3 import BitVec
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"""
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Rule:
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MOD(MUL(X, Y), A) -> MULMOD(X, Y, A)
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given
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A > 0
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A & (A - 1) == 0
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"""
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rule = Rule()
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n_bits = 8
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# Input vars
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X = BitVec('X', n_bits)
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Y = BitVec('Y', n_bits)
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A = BitVec('A', n_bits)
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# Non optimized result
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nonopt = MOD(MUL(X, Y), A)
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# Optimized result
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opt = MULMOD(X, Y, A)
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rule.require(A > 0)
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rule.require(((A & (A - 1)) == 0))
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rule.check(nonopt, opt)
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@ -1,4 +1,4 @@
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from z3 import BitVecVal, BV2Int, If, LShR, UDiv, ULT, UGT, URem
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from z3 import BitVecVal, BV2Int, If, LShR, UDiv, ULT, UGT, URem, ZeroExt, Extract
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def ADD(x, y):
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return x + y
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@ -18,6 +18,12 @@ def SDIV(x, y):
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def MOD(x, y):
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return If(y == 0, 0, URem(x, y))
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def MULMOD(x, y, m):
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return If(m == 0, 0, Extract(x.size() - 1, 0, URem(ZeroExt(x.size(), x) * ZeroExt(x.size(), y), ZeroExt(m.size(), m))))
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def ADDMOD(x, y, m):
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return If(m == 0, 0, Extract(x.size() - 1, 0, URem(ZeroExt(1, x) + ZeroExt(1, y), ZeroExt(1, m))))
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def SMOD(x, y):
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return If(y == 0, 0, x % y)
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