2021-01-21 15:20:22 +00:00
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from opcodes import SHL, SIGNEXTEND
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2021-08-09 15:36:19 +00:00
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from rule import Rule
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2021-01-21 15:20:22 +00:00
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from z3 import BitVec, LShR, ULE
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2021-08-09 15:36:19 +00:00
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"""
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Rule:
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SHL(A, SIGNEXTEND(B, X)) -> SIGNEXTEND((A >> 3) + B, SHL(A, X))
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given return A & 7 == 0 AND A <= WordSize AND B <= WordSize / 8
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"""
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n_bits = 256
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# Input vars
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X = BitVec('X', n_bits)
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Y = BitVec('Y', n_bits)
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A = BitVec('A', n_bits)
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B = BitVec('B', n_bits)
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rule = Rule()
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rule.require(A & 7 == 0)
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rule.require(ULE(A, n_bits))
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rule.require(ULE(B, n_bits / 8))
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rule.check(
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SHL(A, SIGNEXTEND(B, X)),
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SIGNEXTEND(LShR(A, 3) + B, SHL(A, X))
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)
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