2021-01-21 15:20:22 +00:00
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from opcodes import AND, SHR
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2019-06-13 14:43:11 +00:00
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from rule import Rule
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2021-01-21 15:20:22 +00:00
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from z3 import BitVec, BitVecVal, ULT
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2019-06-13 14:43:11 +00:00
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"""
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Rule:
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SHR(B, AND(X, A)) -> AND(SHR(B, X), A >> B)
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SHR(B, AND(A, X)) -> AND(SHR(B, X), A >> B)
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Requirements:
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B < BitWidth
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"""
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rule = Rule()
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n_bits = 128
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# Input vars
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X = BitVec('X', n_bits)
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A = BitVec('A', n_bits)
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B = BitVec('B', n_bits)
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# Constants
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BitWidth = BitVecVal(n_bits, n_bits)
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# Requirements
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rule.require(ULT(B, BitWidth))
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# Non optimized result
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2021-01-21 15:17:01 +00:00
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nonopt_1 = SHR(B, AND(X, A))
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nonopt_2 = SHR(B, AND(A, X))
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2019-06-13 14:43:11 +00:00
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# Optimized result
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2021-01-21 15:17:01 +00:00
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Mask = SHR(B, A)
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opt = AND(SHR(B, X), Mask)
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2019-06-13 14:43:11 +00:00
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rule.check(nonopt_1, opt)
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rule.check(nonopt_2, opt)
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